Chinese FPGA Vendors, Development Boards and Development Tools

Disclosure: The research for this post was conducted and the post was written by OpenAI’s GPT 6.1 Sol model under my guidance. I reviewed the research and the text.

I started this research for my own use and decided to publish it as a post because it may be useful to others exploring Chinese FPGA devices and development boards.

This post compares Chinese FPGA devices and development boards with the hardware classes represented by the Digilent Arty A7-100T, Digilent Arty Z7-20, AMD/Xilinx KR260, KV260 and Terasic DE25-Nano. The focus is on programmable logic with external DDR memory, useful expansion interfaces and development software accessible to hobbyists.

The comparison covers Gowin, Pango, Anlogic and Fudan Micro. It separates FPGA-only boards from devices with hard application processors, then documents software costs and licensing. It also includes the next larger device tier, such as Pango PG2L200H and PG2K400 and Fudan FMQL45/FMQL100, to compare platforms on both sides of the Kria K26’s capacity. Small Tang Nano-class boards are outside this survey.

Specifications, prices and licensing were checked on 11 October 2026. Prices are in USD; converted amounts are approximate. Buying links identify the particular retailer and package rather than a universal board price.

The reference boards and their FPGAs

The Arty A7 provides an FPGA and external memory. The Arty Z7 adds a hard Arm processor system. The KR260 and KV260 use the same K26 system-on-module, with different carrier boards for robotics and vision. The DE25-Nano uses an Altera Agilex 5 SoC with Cortex-A76 and Cortex-A55 application processors.

Sources: Digilent’s Arty A7 specifications, AMD’s 7-series CLB resource table, Digilent’s Arty Z7 specifications and LUT-count table, and AMD’s K26 programmable-logic specification and K26 processor specifications. External K26 memory is documented in the KR260 product brief.

DE25-Nano sources: Terasic board specifications, Altera’s E-Series resource and processor tables and DSP-block configurations. Each variable-precision DSP block supports two 18×19 multipliers.

The Arty A7 has 10/100 Ethernet, four Pmod connectors and Arduino headers. The Arty Z7 adds Gigabit Ethernet, HDMI input/output and USB host connectivity. The KR260 and KV260 expose different Ethernet, camera and expansion interfaces; equal FPGA resources do not make their carrier boards interchangeable.

The DE25-Nano has Gigabit Ethernet, HDMI output, a two-lane MIPI camera connector, USB 2.0, two 40-pin GPIO headers and onboard USB-Blaster III programming. Its LPDDR4 comprises a 1 GB FPGA-side bank and a 1 GB HPS bank accessible from the FPGA. Terasic lists USD 248, or USD 207 academic pricing, on its product and ordering page.

Reading the resource counts

The AMD references extend from roughly 53K to 117K six-input LUTs. The DE25-Nano adds an Agilex 5 reference with 46,800 adaptive logic modules (ALMs), advertised as 138,060 equivalent logic elements (LEs). ALMs and equivalent LEs are different resource counts from LUT6; the reference range is not a numeric cutoff that can be applied directly to every vendor.

A LUT4, LUT5 and LUT6 implement functions with different numbers of inputs. Vendors also publish normalized “logic cell,” “logic element” or “LUT4-equivalent” counts. The tables retain each vendor’s terminology rather than multiplying it into a claimed AMD equivalent. The achievable size and clock rate of a design depend on synthesis, routing and the architecture.

DSP blocks differ too: the Gowin devices below have 18×18 multipliers, while the K26 uses DSP48E2 blocks with 27×18 multipliers. Block RAM is memory inside the FPGA; the DDR capacity in a board listing is external memory. A chip’s transceivers, memory controllers and hard interfaces are usable only where the fitted package, board routing and development tools support them.

FPGA-only boards: comparison with the Arty A7

These boards have no hard application CPU. A soft CPU can be implemented in their fabric, consuming FPGA resources.

The list spans the Arty A7-100T resource range and a larger FPGA tier for comparison with K26’s programmable logic.

The Tang Mega 60K documentation confirms the absence of a hard CPU. Sipeed documents a lane-routing difference that limits PCIe on the NEO Dock to PCIe 2.0 ×1 for this module. Nextitek lists a four-week production time; its wholesale amount is not a confirmed single-board retail checkout price.

The two ALINX boards use different Pango generations. The AXPGL50H uses LUT5 fabric; the AXP100B uses LUT6 fabric. At 66,600 LUT6 and 240 DSP blocks, PG2L100H has a similar LUT count to the Arty A7-100T’s 63,400 LUT6 and 240 DSP blocks. That comparison describes resources, without establishing identical timing, IP or software support. Pango’s Logos and Logos2 tables document the device differences.

Milianke’s resource page names the PH1A90 board and describes obtaining its files through account registration and customer-service activation. The price displayed on that resource page is for download access, not the board.

The AXP201 listing shows USD 374 in the purchase field and USD 264 in its product matrix; the table uses the purchase field. Its PG2L200H has 159,800 LUT6 and 740 DSP blocks. The fitted FBB484 package exposes four transceivers; Pango’s family maximum of 16 applies to a larger package. See the Logos2 device and package tables.

FPGA resources

Sources: Sipeed Mega 60K, Pango Logos, Pango Logos2 and Anlogic’s PH1A family. Anlogic’s resource table is also available in its DS900 datasheet, mirrored by a component supplier.

Arm processor-plus-FPGA boards: comparison with the Arty Z7, Kria and DE25-Nano

These devices contain hard Arm application processors as well as programmable logic. The processor architecture, boot software, memory system and FPGA tools differ from those on the reference boards.

Puzhi’s manufacturer specifications are linked here for PZ7020F-KFB and PZ7020SF-FL-KFB. The Inipro prices include the retailer’s stated customs duty and VAT.

The AXK100 seller page has an inconsistent price: the purchase field shows USD 254, while its product matrix shows USD 236. The table uses the purchase field. Its part-number information also differs between the matrix and ALINX’s module guide, so the fitted package needs confirmation. Anlogic’s AD101 overview describes two DDR3L devices but its capacity notation is ambiguous; no total capacity is inferred here.

Larger SoC boards

These are the next larger family tiers beyond PG2K100 and FMQL20. Their published LUT counts exceed K26’s, while their CPU systems, DSP resources and memory configurations differ.

Pango’s Kosmo2 device table lists 540 blocks of 36 Kbit RAM for PG2K400. ALINX’s SOM guide identifies the LUT6 architecture and eight transceivers in the K400 module’s package. Puzhi lists 19.2 Mbit block RAM for FMQL45 and 26.5 Mbit for FMQL100 on the board pages linked above. The Puzhi prices include Inipro’s stated customs duty and VAT.

There is a PCIe-width discrepancy for AXK400: ALINX’s board manual describes a PCIe ×4 connector, while the retailer lists PCIe 3.0 ×8. The chip supports Gen3 ×8, but that does not establish eight routed lanes on this carrier. The purchased board revision and lane routing need confirmation.

SoC resources and processor differences

Sources: Pango Kosmo2 device table, ALINX SOM guide, Anlogic’s DR1 description, MYIR’s DR1M90 specifications and Puzhi’s FMQL20, FMQL45 and FMQL100 board specifications.

There is a resource-count discrepancy for PG2K100: Pango currently lists 53,600 LUTs and 256 APM blocks, while ALINX’s SOM guide lists 54,000 LUT6 and 220 APM blocks. The table attributes the current figures to the chip vendor rather than treating the sources as identical. Pango also lists no hard high-speed transceivers or hard PCIe for PG2K100; features of the larger PG2K400 must not be attributed to it.

RISC-V processor-plus-FPGA boards

These boards also combine a hard application processor with FPGA fabric, but their CPU architecture differs from the Arm-based Arty Z7, Kria and DE25-Nano platforms.

Sources: Tang Mega 138K documentation, Anlogic’s DR1 announcement and AD102 specifications. Nextitek lists a four-week production time for the 138K package.

The regular Mega 138K in this table uses the PG484A package. The Mega 138K Pro uses a different package and needs the Standard edition of GOWIN EDA. These models have different software requirements despite sharing the 138K name.

How close are these platforms to KR260 and KV260?

The K26 combines 117,120 LUT6, 1,248 DSP blocks, UltraRAM, quad Cortex-A53, dual Cortex-R5F, 4 GB DDR4 and a hard H.264/H.265 video codec. Its two starter kits also have AMD board files and software support for their specific carriers. AMD documents the K26 resources and KR260 board flow.

PG2K100 shares the Cortex-A53 application-processor family, but has two cores and substantially fewer DSP blocks. The next tier, PG2K400, has about 1.86 times K26’s LUT6 count, with 900 versus 1,248 DSP blocks and two application CPU cores. FMQL100 combines quad Cortex-A53 with larger published LUT and DSP counts than K26, but the Puzhi board has separate DDR3 banks and different hard blocks. FMQL20 has the FPGA resource counts of the Arty Z7-20 class and Cortex-A7 processors. DR1M90 uses Cortex-A35 processors. The Mega 138K has a hard RISC-V processor and LUT4 fabric. None of the boards researched here was verified to match the complete K26 combination.

Matching a board’s DDR capacity or advertised logic count does not establish a replacement for a Kria application. Bitstreams, processor boot code, Linux board support, camera/display pipelines and hardware acceleration IP are specific to the target platform.

Development tools and free-license status

Here, a free FPGA flow means synthesis, placement, routing, bitstream generation and programming without a software fee. Simulation, processor development and optional IP cores are separate parts of the workflow.

Gowin

Sipeed’s installation guide explicitly covers free Education-edition use for the Mega boards listed here and distinguishes the 138K Pro. The Gowin download page provides the vendor software. Sipeed also documents B/C device revisions and the device-version setting needed for C-revision chips.

Project Apicula provides an open source Gowin flow using Yosys, nextpnr, bitstream packing and programming tools. Its introductory supported-board list does not establish a complete open flow for the Mega 60K or 138K, including their DDR and other hard blocks. The verified free implementation flow for these boards in this survey is the vendor Education edition.

Pango

PDS Lite explicitly names Logos PGL50H and smaller devices. Its page advertises a free three-year trial without a license file. The full PDS download page separately provides a license application. These statements do not establish free full-PDS support for PG2L100H, PG2L200H, PG2K100 or PG2K400.

Anlogic

Anlogic’s TangDynasty overview describes the FPGA implementation tools. FutureDynasty supports Arm and RISC-V processor-project compilation and debugging, including DR1. It is a separate role from FPGA synthesis and routing.

The technical-support FAQ describes free TD licenses generally lasting six months and replacement licenses. The download portal lists TD, SDKs, board images and license sections, with registration and permission requirements for some resources. The older free-license documentation alone does not confirm every PH1A90/DR1 device, required IP or current release.

Fudan Micro

Fudan’s product overview names Procise and Vulture. Public sources reviewed for the FMQL20, FMQL45 and FMQL100 boards did not establish a free hobbyist license for the complete implementation flow. Software names appearing in board examples do not prove that an AMD license or installer can generate a supported Fudan bitstream.

The reference boards’ software

For context, Vivado ML Standard 2025.1 lists XC7Z020 and Kria support without a license requirement; Digilent also documents free WebPACK support for the Arty A7-100T. See AMD’s versioned supported-device table and Digilent’s Arty A7 page.

Starting with Vivado 2026.1, AMD offers a free BASIC tier with annual license renewal. AMD’s current FAQ says Kria SOM kits receive a CORE voucher, and the licensing page describes development-kit subscriptions lasting one year. Those terms differ from the earlier license-free Standard edition. Sources: AMD licensing options and licensing FAQ.

The DE25-Nano uses Quartus Prime Pro Edition. Altera documents a no-cost license for Agilex 5 E-Series devices, obtainable through the Quartus Pro license-setup dialog. This device-specific license does not establish free access to every Quartus Pro device or optional IP core. See Altera’s no-cost licensing instructions.

Shared free simulation tools

Icarus Verilog, Verilator and GTKWave can be used for HDL simulation and waveform inspection. Vendor primitives, encrypted IP and processor-system models can require vendor-specific simulation support. openFPGALoader supports programming many devices and boards; programming support alone is not a synthesis-to-bitstream flow.

Scope and price notes

This survey excludes the Tang Nano range, AGM AG1280/AG10K examples and smaller SDRAM-only boards. The upper comparison tier includes PG2L200H, PG2K400, FMQL45 and FMQL100. These are larger alternatives within the surveyed families, rather than a strict upper limit at K26’s LUT count. Other Fudan FPGA-only platforms, including 410T and 690T, are outside the purchase comparison.

The Tang Mega prices are converted from Nextitek’s VND listings. The Puzhi prices are converted from Inipro’s KRW listings. Pango and Duyuan prices are already listed in USD. A missing price means that a public amount for the identified package was not verified; it is not an estimate.

Conversions use the latest published reference rates available on 11 October 2026, dated 9 October 2026: EUR 1 = USD 1.1206 = KRW 1,503.27, from the ECB, and USD 1 = VND 25,629, the average interbank rate published by NCB. KRW amounts are converted through EUR and rounded to two decimal places.

Shipping, destination taxes, import charges and payment-provider exchange rates can change the total. Module-only and module-plus-carrier packages have different contents; the availability of a programmer, power supply, schematics, examples and processor SDK depends on the specific package and seller.